||8 Jun 2021 Concall
||A contribution describing the issue further is available at: https://www.ieee802.org/1/files/public/docs2021/maint-regev-scheduled-traffic-race-condition-0421-v02.pdf. It was agreed that there are issues with the state machines that need to be addressed. One suggestion was to break apart the SET_CYCLE_START_TIME state in the 188.8.131.52 Cycle Timer state machine into new states for each of the conditions described in the SetCycleStartTime() procedure. Then an explicit (non-UTC) transition into those states could be identified. It was also pointed out that Figure 8-18, which shows the high-level relationship between state machines in this area of the document is incomplete. The 184.108.40.206 List Config state machine is not shown in this figure and it is precisely the variables used to interlock this machine with the Cycle Timer state machine that is creating the issue. So, Figure 8-18 must also be updated. A final suggestion was made that text should be included that describes the expectations and assumptions about timing delays in reacting to events that trigger state machine transitions. It was agreed to continue discussing the issue and a future contribution will be created to reflect the current ideas discussed on the issue.
||Technical experts review